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The Arithmetic Logic Unit (ALU)

Discrete Mathematics · Chapter 13: Boolean Algebra and Logic CircuitsSection 13.5 · lesson 85 of 8710 min · free with a free account

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In this lesson

Where a processor's computing actually happens.

  • Place the ALU in the fetch-decode-execute cycle
  • Read its result and status flags
  • Trace addition through a ripple-carry adder
  • Explain parallel bitwise logic and opcode selection

Transcript

Everything said in the video, section by section (1,493 words). Read along, or search it.

Boolean Algebra and Logic Circuits

The Arithmetic Logic Unit (ALU)

This section steps back from single gates to the unit where a processor's computing actually happens, the arithmetic logic unit, or ALU. We'll place it inside the CPU, read the status flags it produces, and trace an addition through its adder. Then we'll see why bitwise logic runs in parallel, and how one instruction code picks the output.

The Opening Problem

One Unit, Almost Every Instruction

Every time a processor runs an instruction like add these two numbers, or check whether this bit is set, the actual computation happens in one component. That component is the arithmetic logic unit. The earlier sections built the Boolean tools that make it possible. This section works at the system level. Not what a single AND gate does, but how millions of gates are organized into one unit the CPU calls on for essentially every instruction. That covers a spreadsheet's sum, a game engine's collision check, and a large language model's matrix multiplication. The gate-level wiring of the adders inside is section thirteen point six. Here, the ALU is a system, described the way a datasheet describes a chip.

13.5.1

The ALU's Role in the CPU

A CPU repeatedly runs a fetch, decode, execute cycle. It fetches the next instruction from memory, and decodes which operation that instruction specifies. Then it executes it. For anything that computes, like arithmetic, comparisons or bitwise logic, executing means routing operands into the ALU and reading back the result. Formally, an ALU takes two n-bit operands, A and B, together with an opcode that says which operation to perform. It produces an n-bit result, along with a small set of status flags that describe properties of that result.

Figure 13.5.1

The ALU in the Data Path

Here's where the ALU sits in the data path. The control unit decodes the instruction's opcode, and sends it to the ALU. The register file supplies the two operands, A and B, and receives the result. The ALU computes the result and its status flags. And those flags feed back to the control unit, which uses them to decide whether any conditional branch should be taken.

Status Flags

4 Bits About Every Result

Four status flags are standard on nearly every real ALU. The zero flag, Z, is set when the result is all zeros. The carry flag, C, is set when an addition carries out of the most significant bit, or a subtraction needs a borrow. The overflow flag, V, is set when a signed result is too large to represent correctly. And the sign flag, N, is simply a copy of the result's most significant bit. The control unit reads these flags to decide, for instance, whether a jump if equal, or jump if greater, instruction actually jumps.

Worked Example

ADD R1, R2, R3

Here's an example with four-bit registers. The instruction ADD R one, R two, R three runs. R two holds zero one zero one, which is five, and R three holds zero zero one one, which is three. The control unit decodes the ADD opcode, and routes the two registers into the ALU. Out comes one zero zero zero, which is eight. The zero flag is zero, because the result isn't zero. And the carry flag is zero, because nothing carried out of the top bit. As an unsigned number, eight fits in four bits. Now look at the top bit of the result. It's one. So the sign flag, which copies that bit, is one. And read as a signed four-bit number, one zero zero zero is minus eight. Two positive numbers added to give a negative one, so the overflow flag is set too. The source lists both of those flags as zero, but that's not right. Signed four-bit values only run from minus eight to seven, so five plus three overflows. That's the real lesson of the flags. The same four bits mean eight to an unsigned instruction, and minus eight to a signed one. The flags report on both readings.

13.5.2

Adders as Building Blocks

Binary addition works exactly like grade-school column addition. Add the least significant digits, carry into the next column if needed, and repeat. An ALU's adder is organized the same way, from two small building blocks. For now, only their inputs and outputs matter. A half adder takes two input bits, and produces a sum bit and a carry-out bit. A full adder takes three input bits, two operand bits and a carry-in, and produces a sum bit and a carry-out. A ripple-carry adder chains n full adders together. Each stage's carry-out is wired to the next stage's carry-in, so together they add two n-bit numbers.

Table 13.5.1

Tracing 0101 + 0011

Let's trace five plus three through a four-stage ripple-carry adder, with bit zero as the least significant. Stage zero adds one and one, with no carry in. The sum bit is zero, and it carries one. Stage one adds zero and one, plus that carry. Sum zero, carry one. Stage two adds one and zero, plus the carry. Again sum zero, carry one. Stage three adds zero and zero, plus the carry. Sum one, carry zero. Reading the sums from stage three down to stage zero gives one zero zero zero, which is eight. And the final carry-out, zero, becomes the carry flag.

Figure 13.5.2

A 4-Bit Ripple-Carry Adder

Here's the chain that produced that trace. Four full adders sit side by side, from F A zero on the right of the number, to F A three. The carry-in to the first stage is zero. Each stage takes its pair of operand bits from above, and passes its carry-out along to the next stage. Each stage's sum bit drops out below. And the carry-out of the last stage becomes the ALU's carry flag.

When the Sum Doesn't Fit

Carry Out, and the Cost of Rippling

What if the true sum doesn't fit? Take twelve plus seven, which is nineteen. That needs five bits. The four-bit adder still produces a four-bit result, zero zero one one, which is three, plus a final carry-out of one. That carry-out becomes the carry flag. It's the CPU's only hardware signal that the true result didn't fit in the register. This short program confirms both cases. Five plus three gives eight with no carry, and twelve plus seven gives three with a carry of one. There's a cost to rippling. Each stage has to wait for the previous stage's carry, so the delay grows with the width of the register. Wider ALUs, thirty-two or sixty-four bits, often use a carry-lookahead adder instead. It adds extra logic to compute carries more directly, trading more circuitry for lower latency.

13.5.3

Bitwise Logic Runs in Parallel

Bitwise operations, AND, OR, XOR and NOT, behave completely differently in hardware. Each output bit depends only on the input bits at that same position, never on its neighbors. So an n-bit bitwise operation is just n independent copies of one simple circuit, all working at once, with no carries passed between them. Here's a common technique called bitmasking. To keep only the lower four bits of the byte for two hundred fourteen, AND it with a mask that has ones in those positions. Each output bit is the AND of the two bits directly above it, giving zero zero zero zero zero one one zero, which is six. With no carry to wait for, all eight AND gates evaluate in parallel. That's one reason graphics pipelines and machine learning accelerators are built from vast numbers of these bit-parallel units.

13.5.4

The Opcode Picks the Output

So how does the ALU choose what to do? A real ALU computes several candidate results at once: the adder's sum, the AND, the OR, the XOR, and so on. Then a multiplexer, a circuit that outputs one of several inputs based on a selector signal, uses the opcode to pick exactly one. Here's a simplified scheme with a two-bit opcode, using A equals zero one zero one and B equals zero zero one one. Opcode zero zero selects ADD, giving one zero zero zero. Zero one selects AND, giving zero zero zero one. One zero selects OR, giving zero one one one. And one one selects XOR, giving zero one one zero. All four candidates exist inside the hardware the moment A and B arrive. Only the opcode decides which one the rest of the CPU ever sees. So the ALU is one system, not four separate circuits rewired on demand. The opcode is nothing more than a selector switch on the output.

Takeaways

One System, Many Paths

To summarize. The ALU carries out the execute step. It takes two operands and an opcode, and produces a result plus the status flags zero, carry, overflow and sign. Addition is a chain of full adders, each passing its carry-out to the next, just like carrying a digit in long addition. Bitwise logic runs as independent, parallel per-bit circuits, which is part of why it's faster than addition on wide data. And the ALU computes several candidates in parallel, letting the opcode drive a multiplexer that selects the output. Here's something to think about. A bitwise AND finishes in one gate delay, but a ripple-carry addition can take as many as n. So why would a designer accept that slower worst case? And what does the existence of carry-lookahead adders suggest about how engineers trade speed against circuit complexity?

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FAQ

Questions students ask us

About The Arithmetic Logic Unit (ALU)

What does the ALU do in the fetch-decode-execute cycle?
The ALU performs the execute step for any instruction that computes, such as arithmetic, comparisons, or bitwise logic. After the CPU fetches and decodes an instruction, the control unit sends the opcode to the ALU, and the register file supplies operands A and B. The ALU returns an n-bit result plus status flags, which the control unit uses to decide conditional branches.
What do the zero, carry, overflow, and sign flags mean on an ALU?
The four flags describe the result: Z is set when the result is all zeros, C when an addition carries out of the top bit or a subtraction borrows, V when a signed result is too large to represent, and N copies the result's most significant bit. For 4-bit 0101+0011=1000, Z and C are 0, but N and V are 1, since signed 1000 is -8.
How does a ripple-carry adder add two binary numbers like 0101 + 0011?
A ripple-carry adder adds bit by bit with full adders, passing each carry-out into the next stage's carry-in. For 0101+0011, stages 0, 1, and 2 each give sum 0 and carry 1, and stage 3 gives sum 1 and carry 0. Reading the sums from stage 3 down gives 1000, which is 8. The final carry-out, 0, becomes the carry flag.
How does an ALU choose between ADD, AND, OR, and XOR, and why is bitwise logic parallel?
The opcode drives a multiplexer that selects one of several results the ALU has already computed at once. With A=0101 and B=0011, opcode 00 selects ADD (1000), 01 selects AND (0001), 10 selects OR (0111), and 11 selects XOR (0110). Bitwise operations run in parallel because each output bit depends only on the input bits at its own position, so no carries are passed.

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